1. Field of Invention
The present invention relates generally to the field of Structured ASICs. Embodiments of the present invention relate to a microcontroller for a Structured ASIC that is primarily used for testing the memory and logic of the Structured ASIC.
2. Description of Related Art
The present invention relates generally to an improved Structured ASIC (Structured Application Specific Integrated Circuit). Broadly defined, structured application-specific integrated circuits (ASICs) may attempt to reduce the effort, expense and risk of producing ASICs by standardizing portions of the physical implementation across multiple products. By amortizing the expensive mask layers of the device across a large set of different designs, the non-recurring engineering (NRE) for a customized ASIC seen by a particular customer, which are one-time costs that do not depend on the number of units sold, can be significantly reduced. There may be additional benefits to the standardization of some portion of mask set, which may include improved yield through higher regularity and/or reduced manufacturing time from tape-out to packaged chip.
ASICs can be broken down further into a full-custom ASIC, a Standard Cell-based ASIC (standard-cell), a Structured ASIC, and a gate array ASIC. At the opposite end of an ASIC is a field-programmable gate array (FPGA), an integrated circuit designed to be configured by the customer or designer after manufacturing in the field using software commands rather than at a foundry or IC fab. Other non-ASICs include simple and complex PLDs (Programmable Logic Devices), and off-the-shelf small and medium scale IC components (SSI/MSI). Further classifications include a Configurable Logic Block (CLB). A configurable logic block (CLB) may be an element of field-programmable gate array (FPGA), structured application-specific integrated circuit (ASIC) devices, and/or other devices. CLBs may be configured, for example, to implement different logic cells (combinational, such as NANDs, NORs, or inverters, and/or sequential, such as flip-flops or latches).
A full-custom ASIC customizes every layer in an ASIC device, which can have 10 to 15 layers, requiring in a lithography process 10 to 15 masks. Since the customized design of the ASIC occurs at the transistor level, and modern ASICs have tens if not hundreds of millions of transistors, a full-custom ASIC is typically economically feasible only for applications that required millions of units. An example of such an application is the cell phone digital modem or a flat panel television video processing device.
In a standard cell ASIC, circuits are constructed from predefined logic components known as cells. Designers work at the gate level not the finer transistor level, simplifying the process. The fab manufacturing the device provides a library of basic building blocks that can be used in the cells, such as basic logic gates, combinational components (and-or-inverter, multiplexer, 1-bit full adder), and basic memory, such as D-type latch and flip-flop. A library of other function blocks such as adder, barrel shifter and random access memory (RAM) may also exist. While the layout of each cell in a standard cell is predetermined, the circuit itself has to be uniquely constructed by connecting all layers to one another and the cells within each layer in a custom manner, which takes time and effort.
A register is a standard component in an ASIC, and is a group of flip-flops that stores a bit pattern. Registers can hold information from components or hold state between iterations of a clock so that it can be accessed by other components, to allow I/O synchronization, handshaking data between clock domains, pipelining, and the like.
In a gate-array ASIC, the level of abstraction is one level higher than a standard cell, in that each building block in a gate array is from an array of predefined cells, known as a base cell, which resembles a logic gate. Since location and type of cell is predetermined, gate-array ASICs can be manufactured in advance in greater quantities and inventoried for use later. A circuit is manufactured by customizing the interconnect between these cells, which is done at the metal interconnect masks. As in gate level ASICs, typically 3 to 5 metal layers have to be customized to specify the interconnect required to complete the circuit, which simplifies the manufacturing process.
In a Structured ASIC the level of abstraction is somewhere between the full-custom ASIC and the FPGA. In a Structured ASIC there may be a dozen or more metal layers, but in many structured ASICs not all metal layers need be for routing, and some layers may be pre-routed, and only the top layers are used for routing. The idea behind the structured ASIC is that the most of the layers are predefined; only a few metal or via layers are available for customization. An extreme case is the eASIC structured ASIC, assignee to this invention: only a single via layer is available for customization, and all the other layers are predefined. This reduces the complexity of the manufacturing process, since non-recurring engineering costs are much lower, as photolithographic masks are required only for the fewer metal layers not for every layer, and production cycles are much shorter, as metallization is a comparatively quick process. The metal layers may be interconnected with one another at select vertical holes called vias that are filled with conductive material, which can be called the ‘via’ metal layer, and thus be configurable at this layer, or ‘via configurable’. If the logic fabric comprising the Structured ASIC is configured with traditional IC optical lithography involving photolithographic masks, it can be thought of as “mask programmable”. In some designs, such as by the present assignee to this invention, eASIC Corporation, the customizable metallization layers may be reduced to a few or even a single via layer where the customization is performed, see by way of example and not limitation U.S. Pat. No. 6,953,956, issued to eASIC Corporation on Oct. 11, 2005; U.S. Pat. No. 6,476,493, issued to eASIC Corporation on Oct. 11, 2005, and Nov. 5, 2002; and U.S. Pat. No. 6,331,733, issued to eASIC Corporation on Dec. 18, 2001; all incorporated herein by reference in their entirety.
A complex field programmable device is a versatile non-ASIC, as the generic logic cells can sometimes be more sophisticated than ASIC cells, and the interconnect structure, can be programmable in the field using software rather than at a fab using for example photolithographic masks. A complex field programmable device can be re-programmed to a different circuit in hours, rather than only being programmable once at a fab like an ASIC. A complex field programmable device can be broadly divided into two categories, a Complex Programmable Logic Device (CPLD) and a Field Programmable Gate Array (FPGA). The logic cell of a CPLD can be more complex than an FPGA, and has a D-type flip-flop and a programmable logic device semiconductor such as a PAL™ type programmable logic device semiconductor, with configurable product terms. The interconnect of a CPLD is more centralized, with fewer concentrated routing lines. A FPGA logic cell is smaller, with a D-type flip-flop and a small Look Up Table (LUT), a multi input and single output block that is widely used for logic mapping, or multiplexers for routing signals through the interconnect and logic cells. The FPGA design that defines a circuit is stored in RAM, so when the FPGA is powered off, the design for the circuit disappears. When the FPGA is powered back up, one must reload the circuit design from non-volatile memory.
A simple PLD, historically called a programmable logic device, is much more limited in application, as they do not have a general interconnect structure. Today these devices are relatively rare by themselves and are now used as internal components in an ASIC or CPLD. Likewise, off-the-shelf small and medium scale IC components (SSI/MSI) are rarely used anymore, as they are first generation devices such as the 7400 series transistor-transistor logic (TTL) manufactured by various companies used in the 1960s and 70s to build computers. These components are no longer supported by modern EDA (Electronic Design Automation) software and have very limited functionality.
A complex field programmable device can be thought of as a form of programmable logic fabric. One such programmable logic fabric is a SRAM programmable Look-Up Table (LUT) technology that forms the basis of Field Programmable Gate Arrays and Complex Programmable Logic Devices. The programmable fabric technology allows synthesis of a logic design described in a Hardware Description Language (HDL) to be synthesized on to the logic fabric in order to perform the required logic function. The logic fabric includes memory blocks, embedded multipliers, registers and Look-Up Table logic blocks. Interconnect between logic elements is also SRAM programmable. As the state of the SRAM is deleted when powered off, the function of the programmable logic fabric incorporating SRAM can be changed.
ASIC design flow as a whole is a complex endeavor that involves many tasks, as described further herein, such as: logic synthesis, Design-for-Test (DFT) insertion, Electric Rules Check (ERC) on gate-level netlist, floorplan, die size, I/O structure, design partition, macro placement, power distribution structure, clocks distribution structure, preliminary check, (e.g., IR drop voltage drop, Electrostatic Discharge (ESD)), placement and routing, parasitic extraction and reduction (parasitic devices), Standard Delay Format (SDF) timing data generated by EDA tools, various checks including but not limited to: static timing analysis, cross-talk analysis, IR drop analysis, and electron migration analysis.
At the first step in the ASIC design flow, the design entry step, the circuit is described, as in a design specification of what the circuit is to accomplish, including functionality goals, performance constraints such as power and speed, technology constraints like physical dimensions, and fabrication technology and design techniques specific to a given IC foundry. Further in the design entry step is a behavioral description that describes at a high-level the intended functional behavior of the circuit (such as to add two numbers for an adder), without reference to hardware. Next is a RTL (Register Transfer Language) structural description which references hardware, albeit at a high-level of abstraction using registers. RTL focuses on the flow of signals between registers, with all registers updated in a synchronous circuit at the same time in a given clock cycle, which further necessitates in the design flow that the clocks be synchronized and the circuits achieve timing constraints and timing closure. RTL description captures the change in design at each clock cycle. All the registers are updated at the same time in a clock cycle for a synchronous circuit. A synchronous circuit consists of two kinds of elements: registers and combinational logic. Registers have a clock, input data, output data and an enable signal port. Every clock cycle the input data is stored internally and the output data is updated to match the internal data. Registers, often implemented as flip-flops, synchronize the circuit's operation to the edges of the circuit clock signal, and have memory. Combinational logic performs all the logical functions in the circuit and it typically consists of logic gates. RTL is expressed usually in a Verilog or VHDL Hardware Description Language (HDL), which are industry standard language descriptions. A hardware description language (HDL) is a language used to describe a digital system, for example, a network switch, a memory or a flip-flop. By using a HDL one can describe any digital hardware.
A design flow progresses from logical design steps to more physical design steps. Throughout this flow timing is of critical importance and must be constantly reassessed so that timing closure is realized throughout the circuit, since timing between circuits could change at different stages of the flow. Furthermore, the circuit must be designed to be tested for faults. The insertion of test circuitry can be done at the logic synthesis step, where register transfer level (RTL), is turned into a design implementation in terms of logic gates such as a NAND gate. Thus logic synthesis is the process of generating a structural view from the RTL design output using an optimal number of primitive gate level components (NOT, NAND, NOR, and the like) that are not tied to a particular device technology (such as 32 nm features), nor do with any information on the components' propagation delay or size.
Design for testing (DFT) in the context of an integrated circuit (IC) and ASIC is a design technique that makes it easier to test microelectronic hardware though the introduction of features that make testing the hardware for defects easier. DFT includes scan-design (scan-chain design) and various forms of Built-In-Self-Test (BIST). DFT can interface with Automatic Test Equipment (ATE), which is an apparatus that performs tests on a device, known as the Device Under Test (DUT), and DFT conforms to various standards set by standards bodies, such as Joint Test Action Group (JTAG) and the IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture. Joint Test Action Group (JTAG) is the common name for what was later standardized as the IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture. JTAG can be used for IC debug ports. In the embedded processor market, testing through debuggers occurs with JTAG to perform operations like single stepping and breakpointing. JTAG may also be used in a Boundary Scan chain, where the interface to on-chip registers is used to test combinational logic.
In scan-design, registers in a circuit design under test are connected to scan chain circuitry, and a test pattern is applied by shifting it into the scan chains, to access to internal modes of the circuit. A clock signal is pulsed to test the circuit during a capture cycle and the results shifted out of the circuit for analysis. Scan chains can also be used for debugging, when an integrated circuit can be made to go into test mode and the internal state of the circuit can be output or set to a particular state through the use of scan chains. This is sometimes known as “Design for Debug”.
BIST can reduce the complexity associated with DFT in an IC by reducing the need for slower, more expensive external test equipment. One idea behind BIST is that the introduction of an input sequence to the flip-flops, shift registers and/or latches of an ASIC will generate over time a unique signal that can be sampled and stored by the BIST circuitry to check for the presence of errors, with the output accessible through a JTAG/IEEE 1149.1 standard interface.
In logical synthesis the circuit can be manipulated with Boolean algebra. Logical synthesis may be divided into two-level synthesis and multilevel synthesis. Because of the large number of fan-ins for the gates (the number of inputs to a gate), two-level synthesis employs special ASIC structures known as Programmable-Logic Arrays (PLA) and modified Programmable Array Logic (PAL)-based CPLD devices. Multilevel synthesis is more efficient and flexible, as it eliminates the stringent requirements for the number of gates and fan-ins in a design, and is preferred. The multilevel synthesis implementation is realized by optimizing area and delay in a circuit. However, optimizing multilevel synthesis logic is more difficult than optimizing two-level synthesis logic, and often employs heuristic techniques.
Functional synthesis is performed at the design entry stage to check that a design implements the specified architecture. Once Functional Verification is completed, the RTL is converted into an optimized gate level netlist, using smaller building blocks, in a step called Logic Synthesis or RTL synthesis. In EDA this task is performed by third party tools. The synthesis tool takes an RTL hardware description and a standard cell library for a particular manufacturer as input and produces a gate-level netlist as output. The standard cell library is the basic building block repository for today's IC design. Constraints for timing, area, speed, testability, and power are considered. Synthesis tools attempt to meet constraints by calculating the engineering cost of various implementations. The tool then attempts to generate the best gate level implementation for a given set of constraints, target the particular manufacturing process under consideration. The resulting gate-level netlist is a completely structural description with only standard cells at the “leaves” of the design. At logical/RTL synthesis it is also verified whether the Gate Level Conversion has been correctly performed by performing simulation. The netlist is typically modified to ensure any large net in the netlist has cells of proper drive strength (fan out), which indicates how many devices a gate can drive. A driving gate can be any cell in the standard cell library. During compilation of the netlist the EDA tool many adjust the size of the gate driving each net in the netlist so that area and power is not wasted in the circuit by having too large of a drive strength. Buffer cells are inserted when a large net is broken into smaller sections by the EDA tool.
Throughout the logical design state, an EDA tool performs a computer simulation of the layout before actual physical design.
The next step in the ASIC flow is the physical Implementation of the gate level netlist, or physical design, such as system partitioning, floorplanning, placement and routing. The gate level netlist is converted into a geometric representation of the layout of the design. The layout is designed according to the design rules specified in the library for the fab that is to build the digital device. The design rules are guidelines based on the limitations of the fabrication process.
The Physical Implementation step consists of several sub steps: system partitioning, floorplanning, placement and routing. These steps relating to how the digital device is to be represented by the functional blocks, as one ASIC or several (system partitioning), how the functional blocks are to be laid out on one ASIC (floorplanning) and how the logic cells can be placed within the functional blocks (placement) and how these logic cells are to be interconnected with wiring (routing). The file produced at the output of this Physical Implementation is the so-called GDSII file, which is the file used by the foundry to fabricate the ASIC.
Floorplanning involves inputting into a floorplanning tool a netlist that describes the interconnection of ASIC blocks (RAM, ROM, ALU, cache controller, and the like); the logic cells (NAND, NOR, D flip-flop, and so on) within the blocks; and the logic cell connectors (e.g., terminals, pins, or ports). Floorplanning maps the logical description as found in the netlist to the physical description, the floorplan.
The goals of floorplanning are to arrange the ASIC blocks on the silicon chip, to decide the location of the I/O pads, to decide the location and number of the power pads, the type of power distribution, and the location and type of clock distribution. Design constraints in floorplanning include minimizing the silicon chip area and minimizing timing delay. Delay is often estimated from the total length of the interconnect and from an estimate of the total capacitance. Interconnect length and predicted interconnect capacitance is estimated from statistics of previously routed chips, including such factors as net fanout and block size of the circuits in the ASIC.
For any design to work at a specific speed, timing analysis has to be performed throughout the ASIC design flow. One must check using a Static Timing Tool in EDA whether the design is meeting the speed requirements of the specification. Industry standard Static Timing tools include Primetime (Synopsys), which verifies the timing performance of a design by checking the design for all possible timing violations caused by the physical design process.
During placement, for example, timing is effected since the length of an interconnect caused by placement changes the capacitance of the interconnect and hence changes the delay in the interconnect. The goal of an EDA placement tool is to arrange all the logic cells within the flexible blocks on a chip to achieve objectives such as: guarantee the router can complete the routing step, minimize all the critical net delays, make the chip as dense as possible, minimize power dissipation, and minimize cross talk between signals. Modern EDA placement tools use even more specific and achievable criteria than the above. The most commonly used placement objectives are one or more of the following: minimize the total estimated interconnect length, meet the timing requirements for critical nets, and minimize the interconnect congestion.
Algorithms for placement do exist, for example, the minimum rectilinear Steiner tree (MRST) is the shortest interconnect using a rectangular grid. The determination of the MRST is in general an NP-complete problem—which is difficult to solve in a reasonable time. For small numbers of terminals heuristic algorithms exist, but they are expensive in engineering cost to compute. Several approximations to the MRST exist and are used by EDA tools.
In the routing step, the wiring between the elements is planned. A Structured ASIC cross-section has metal layers; in a standard cell ASIC there may be nine metal layers, but in many structured ASICs not all metal layers need be for routing, and some layers may be pre-routed, and only the top layers are used for routing. The metal layers may be interconnected with one another at select vertical holes called vias that are filled with conductive material and/or can be made to conduct, which may be called the ‘via’ connection layer or via metal layer, and thus be configurable at this layer, or ‘via configurable’. If the logic fabric comprising the Structured ASIC is configured with traditional IC optical lithography involving photolithographic masks, it can be thought of as “mask programmable”. The mask for a Structured ASIC is programmed at the vias, and when the Structured ASIC employs via-configurable logic blocks it can be termed a via-configurable logic block (VCLB) architecture. The configuration and programmability of the VCLB architecture of the Structured ASIC may be performed by changing properties of so called “configurable vias”—connections between VCLB internal nodes. A configurable or programmable via may be in one of two possible states: it may be either enabled or disabled. If a programmable via is enabled, then it can conduct a signal (i.e., the via exists and has low resistance). If a via is disabled, then it cannot practically conduct a signal, i.e., the via has very high resistance or does not physically exist. In some designs, such as by the present assignee to this invention, eASIC Corporation, the customizable metallization layers may be reduced to a few or even a single via layer where the customization is performed, see by way of example and not limitation U.S. Pat. No. 6,953,956 issued to eASIC Corporation on Oct. 11, 2005; U.S. Pat. No. 6,476,493, issued to eASIC Corporation on Oct. 11, 2005, and Nov. 5, 2002; and U.S. Pat. No. 6,331,733, issued to eASIC Corporation on Dec. 18, 2001; all incorporated herein by reference in their entirety. Further, a single via layer could be customized without resorting to mask-based optical lithography, but with a maskless e-beam process, as taught by the '956 patent.
During circuit extraction and post layout simulation, a back-annotated netlist is used with timing information to see if the physical design has achieved the objectives of speed, power and the like specified for the design. If not, the entire ASIC design flow process is repeated. In modern EDA tools the delays calculated from a simulation library of library cells used in the design, during physical design steps, are placed in a special file called the SDF (Synopsys Delay Format) file. Each cell can have its own delay based on where in the netlist it is found, what are its neighboring cells, the load on the cell, the fan-in, and the like. Each internal path in a cell can have a different propagation time for a signal, known as a timing arc. The maximum possible clock rate is determined by the slowest logic path in the circuit, called the critical path.
Compounding the problem of delay is that in a synchronous ASIC one must avoid clock skew, and different parts of the ASIC may have different clock domains controlling them, with the wiring nets that establish the clock signal forming a clock net branching out in the form of a clock tree. Establishing this tree, which often requires additional circuitry like buffer cells to help drive the massive clock tree, is called clock tree synthesis. As an ASIC is a synchronous circuit, all the clocks in the clock tree must be in synch and chip timing control achieved, typically by using Phase-Locked Loops (PLLs) and/or Delay-Locked Loops (DLLs). If the clock signal arrives at different components at different times, there is clock skew. Clock skew can be caused by many different things, such as wire-interconnect length, temperature variations and differences in input capacitance on the clock inputs of devices using the clock. Further, timing must satisfy register setup and hold time requirements. Both data propagation delay and clock skew play important parts in these calculations. Problems of clock skew can be solved by reducing short data paths, adding delay in a data path, clock reversing and the like. Thus during the physical synthesis steps, clock synthesis is an important step, which distributes the clock network throughout the ASIC and minimizes the clock skew and delay.
Finally, IP in the form of proprietary third party functionality such as a semiconductor processor may be embedded in an ASIC using soft macros, firm macros and hard macros that can be bought from third parties. A soft macro describes the IP as RTL code and does not have timing closure given the design specification nor layout optimization for the process under consideration. However as RTL code a soft macro can be modified by a designer with EDA tools and synthesized into the designer's library. By contrast, a hard macro is timing-guaranteed and layout-optimized for a particular design specification and process technology but is not portable outside the particular design and process under consideration, but is not represented in RTL code; rather a hard macro is tailored for a particular foundry and closer to GDSII layout. A firm macro falls between a hard macro and a soft macro. Firm macros are in netlist format, are optimized for performance/area/power using a specific fabrication technology, are more flexible and portable than hard macros, and more predictive of performance and area to be used than soft macros. Macros obviate a designer having to design every component from scratch, and are a great time saver. Third party designers favor firm and hard macros since it is easier to hide intellectual property (IP) present in such macros than it is to hide such IP in a soft macro.
Given the above, the pros and cons of standard cell ASICs versus a complex field programmable device such as an FPGA is as follows. The advantages of FPGAs are that they can be easy to design, have shorter development times and thus are faster in time-to-market, and have lower NRE costs. These are also the disadvantages of standard cell ASICs: they can be difficult to design, have longer development times, and higher NRE costs. The disadvantages of FPGAs are that design size is limited to relatively small production designs, design complexity is limited, performance is limited, power consumption is high, and there is a high cost per unit. These FPGA disadvantages are standard-cell advantages, as standard cells support large and complex designs, have high performance, low power consumption and low per-unit cost at a high volume.
A Structured ASIC falls between an FPGA and a Standard Cell-based ASIC in classification and performance. Structured ASIC's are used for mid-volume level designs. In a Structured ASIC the task for the designer is to map the circuit into a fixed arrangement of known cells.
Structured ASICs are closer to standard-cells in their advantages over FPGAs. The disadvantage of structured ASICs compared to FPGAs is that FPGAs do not require any user design information during manufacturing. Therefore, FPGA parts can be manufactured in larger volumes and can exist in larger inventories. This allows the latency of getting parts to customers in the right volumes to be reduced. FPGAs can also be modified after their initial configuration, which means that design bugs can be removed without requiring a fabrication cycle. Design improvements can be made in the field, and even done remotely, which removes the requirement of a technician to physically interact with the system. Given these pros and cons, structured ASICs combine the best features of FPGAs and standard cell ASICS.
Structured ASIC advantages over standard cell ASICs and FPGAs include that they are largely prefabricated, with components are that are almost connected in a variety of predefined configurations and ready to be customized into any one of these configurations. Fewer metal layers are needed for fabrication of a Structured ASIC, which dramatically reduces the turnaround time. Structured ASICs are easier and faster to design than standard cell ASICs. Multiple global and local clocks are prefabricated in a Structured ASIC. Consequently, there are no skew problems that need to be addressed by the ASIC designer. Thus signal integrity and timing issues are inherently addressed, making design of a circuit simpler and faster. Capacity, performance, and power consumption in a Structured ASIC is closer to that of a standard cell ASIC. Further, structured ASICs have faster design time, reduced NRE costs, and quicker turnaround than standard cell ASICs. Thus with structured ASICs the per-unit cost is reasonable for several hundreds to 100 k unit production runs.
A technology comparison between standard cell ASICs, structured ASICs, and FPGAs, respectively, is roughly as follows: generally speaking, and these ratios can change year-by-year and with different process lithographic nodes, there is a ratio of 100:33:1 between the number of gates in a given area for standard cell ASIC's, structured ASICs, and FPGAs, respectively; a ratio of 100:75:15 for performance (based on clock frequency); and a ratio of 1:3:12 for power.
Compared to a field-programmable gate array (FPGA), the unit price of a Structured ASIC solution may be reduced by an order of magnitude due to the removal of the storage and logic required for configuration storage and implementation. The unit cost of a Structured ASIC may be somewhat higher than a full custom ASIC, primarily due to the imperfect fit between design requirements and a standardized base layer, with certain I/O, memory and logic capacities. An ideal ASIC device may combine the field programmability of FPGAs with the power and size efficiency of ASICs or structured ASICs.
An Advanced Microcontroller Bus Architecture (AMBA) is a open standard, on-chip bus specification used in system-on-a-chip (SoC) designs including Structured ASICS. Advanced High-performance Bus (AHB) is a bus protocol introduced in Advanced Microcontroller Bus Architecture version 2 by ARM Ltd. company. AHB provides for single edge clock protocol, split transactions, several bus masters, burst transfers, pipelined operations, single-cycle bus master handover, non-tristate implementations, and large bus-widths (64/128 bit). A simple transaction on AHB can consists of an address phase and a subsequent data phase without wait states. Access to a target device may be controlled through a non-tristate MUX.
A System-in-Package (SiP) are multiple bare dice and/or chip-scale package (CSP) devices, each implementing their own function (e.g., analog, digital, and radio frequency (RF) dice) that are mounted on a SiP common substrate, which is used to connect them together. The substrate and its components are then placed in (or built into) a single package, called an IC (Integrated Circuit) or SiP, which is a traditional two-dimensional (2D) chip. A 2.5D IC/SiP is different from a traditional 2D IC/SiP, and in one type of 2.5D IC a silicon interposer is placed between the SiP common substrate and the dice, where this silicon interposer has through-silicon vias connecting the metallization layers on the upper and lower surfaces of the silicon interposer. The multiple bare dice can be attached to the silicon interposer using micro-bumps, which are about ˜10 um in diameter, and in turn the silicon interposer is attached to the SiP substrate using regular flip-chip bumps, which can be ˜100 um in diameter. Further, a 3D IC/SiP configuration enable designers to achieve higher levels of integration by allowing multiple die to be stacked vertically on top of one another. Wire bonds connect a topmost die with an underlying SiP substrate and allow the topmost die to communicate with a SiP substrate that is covered by an underlying die.
Testing is important in a Structured ASIC. What is needed in the art is a scalable microcontroller network for testing a Structured ASIC, in one of two modes: either through an external source for testing, or internally with a micro-controller or processor, preferably using JTAG signals, and an easy way of switching between the two modes.